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qntm_apss_glink_config qcom,qntm-apss-glink-config
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qcom,tlmm 8@P p ј І џ І D z { summary directconn0 directconn1 . р @ P pinmux qcom,tlmm-pinmux qup0_se0_l0 \ ` qup0_se0_l1 \ ` qup0_se0_l2 \ ` qup0_se0_l3 \ ` qup0_se1_l0 \ ` qup0_se1_l1 \ `
qup0_se1_l2_mira \ `
qup0_se1_l2_mirb \ ` qup0_se1_l3_mira \ ` qup0_se1_l3_mirb \ ` qup0_se2_l0 \ ` qup0_se2_l1 \ ` qup0_se2_l2 \ ` qup0_se2_l3 \ ` qup0_se3_l0 \
` qup0_se3_l1 \ ` qup0_se3_l2 \ ` qup0_se3_l3 \
` qup0_se4_l0 \ ` qup0_se4_l1 \
` qup0_se4_l2 \
` qup0_se4_l3 \ ` qup0_se5_l0 \ ` qup0_se5_l1 \ ` qup0_se5_l2 \ ` qup0_se5_l3 \ ` qup0_se6_l0 \ ` qup0_se6_l1 \ ` qup0_se6_l2 \ ` ! qup0_se6_l3 \ ` " qup0_se7_l0 \ ` # qup0_se7_l1 \ ` $ qup0_se7_l2 \ ` % qup0_se7_l3 \ ` & qup0_se8_l0 \ ` ' qup0_se8_l1 \ ` ( qup0_se8_l2 \ ` ) qup0_se8_l3 \ ` * qup0_se9_l0_mirb \ 0 ` + qup0_se9_l1_mirb \ 1 ` , qup0_se9_l2_mirb \ 2 ` - qup0_se9_l3_mirb \ 3 ` . tlmm-pinctrl
qcom,pinctrl top_qup0_se0_i2c_active n 6 top_qup0_se0_i2c_sleep n 7 top_qup0_se0_spi_active n 8 top_qup0_se0_spi_sleep n 9 top_qup0_se0_uart_active n : top_qup0_se0_uart_sleep n ; top_qup0_se1_i2c_active n
< top_qup0_se1_i2c_sleep n
= top_qup0_se1_spi_active n
> top_qup0_se1_spi_sleep n
? top_qup0_se1_uart_active n
@ top_qup0_se1_uart_sleep n
A top_qup0_se2_i2c_active n B top_qup0_se2_i2c_sleep n C top_qup0_se2_spi_active n D top_qup0_se2_spi_sleep n E top_qup0_se2_uart_active n F top_qup0_se2_uart_sleep n G top_qup0_se3_i2c_active n H top_qup0_se3_i2c_sleep n I top_qup0_se3_uart_active n J top_qup0_se3_uart_sleep n K top_qup0_se4_i2c_active n L top_qup0_se4_i2c_sleep n M top_qup0_se4_uart_active n N top_qup0_se4_uart_sleep n O top_qup0_se5_i2c_active n P top_qup0_se5_i2c_sleep n Q top_qup0_se5_spi_active n R top_qup0_se5_spi_sleep n S top_qup0_se5_uart_active n T top_qup0_se5_uart_sleep n U top_qup0_se6_i2c_active n V top_qup0_se6_i2c_sleep n W top_qup0_se6_spi_active n ! " X top_qup0_se6_spi_sleep n ! " Y top_qup0_se6_uart_active n ! " Z top_qup0_se6_uart_sleep n ! " [ top_qup0_se6_i3c_active n \ top_qup0_se6_i3c_sleep n ] top_qup0_se7_i2c_active n # $ ^ top_qup0_se7_i2c_sleep n # $ _ top_qup0_se7_uart_active n # $ % & ` top_qup0_se7_uart_sleep n # $ % & a top_qup0_se8_i2c_active n ' ( b top_qup0_se8_i2c_sleep n ' ( c top_qup0_se8_spi_active n ' ( ) * d top_qup0_se8_spi_sleep n ' ( ) * e top_qup0_se8_uart_active n ' ( ) * f top_qup0_se8_uart_sleep n ' ( ) * g top_qup0_se9_i2c_active n + , h top_qup0_se9_i2c_sleep n + , i top_qup0_se9_spi_active n + , - . j top_qup0_se9_spi_sleep n + , - . k top_qup0_se9_uart_active n + , - . l top_qup0_se9_uart_sleep n + , - . m tlmm_port@0 qcom,gpio-port P 8 @ ј / tlmm_port@1 qcom,gpio-port P 8 @ ј 0 tlmm_port@2 qcom,gpio-port P 8 @ ј 1 tlmm_port@3 qcom,gpio-port P 8 @ ј 2 tlmm_port@4 qcom,gpio-port P 8 @ ј 3 tlmm_port@5 qcom,gpio-port P 8 @ ј 4 tlmm-interface qcom,gpio-nexus P vџџџр џџџџ x / 0 @ 1 ` 2 3 4 timetick qcom,timetick timer@02002000 qcom,timetick-timer 8 SystemTimer Ћ$ј Ж $ timer@02003000 qcom,timetick-timer 8 0 WakeUpTimer Ћ$ј Ж % icbarb qcom,icbarb clock-controllers qcom,cc clock-controller@41400000 5 qcom,gcc-shikra qcom,cc-shikra qcom,clock-controller 8A@ оGCC_CLK_CTL_REG Р 5 regulators qcom,regulator vdd_mxa qcom,rpm-regulator Э/vcs/vdd_mx м є р %/vcs/vdd_cx/vlvl 8rwcx Rvlvl ] vdd_cx qcom,rpm-regulator Э/vcs/vdd_cx м є р %/vcs/vdd_mx/vlvl 8rwmx Rvlvl ] ipcc
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ј @ ( ? R a x Ш Ѕ < Р р ћ 3 Ш P jK ш Э ч 5 Q i Ѓ П з № # < @ Y < board-id xdefault А aliases & /soc/TOP_QUP_0@4a00000/TOP_QUP_0_SE_1 & /soc/TOP_QUP_0@4a00000/TOP_QUP_0_SE_7 & /soc/TOP_QUP_0@4a00000/TOP_QUP_0_SE_6 #address-cells #size-cells compatible model device_type reg riscv,isa status cpu-power-states #interrupt-cells interrupt-controller phandle power-state-name substate-id min-residency-us exit-latency-us interrupts-extended reg-names riscv,max-priority riscv,ndev interrupt-parent interrupts base-addr basic-setting additional-setting cache-line-size mst-ctrlp-base cache-flush-cmd-offset cache-flush-status-offset cache-flush-addr-offset memory-region irq-conditioning-base plic-mask-offset plic-type-offset plic-clr-offset clint-mask-offset clint-type-offset clint-clr-offset external-interrupt-list nmi-irq-vector-reg nmi-status-reg nmi-cookie-reg nmi-dump-pointer-reg nmi-rom-patch-pre-flush nmi-rom-patch-post-flush feed_period bark_time bite_time clk_freq feed_reg bark_time_reg ctrl_reg wdt_freeze_en_mask wdt_freeze_en_shft wdt_en_mask wdt_en_shft proc proc_printsig proc_logsig proc_enum channel_name host remote endpoint rx_enabled rx_port tx_enabled tx_port supported-hosts remote-host fifo-size mtu-size irq-out qos-max-rate msg-ram-base msg-ram-size remote_ss tx_fifo_id rx_fifo_id smem-this-host smem-version-offset tcsr-base mutex-offsets-data wonce-offsets host-name host-id fflags max-entries dest irq transport remote-ss ch-name options stack-size intents ngpios width egpio interrupt-names summary-targetproc directconn-offset gpio-controller #gpio-cells mux #config-cells configs gpio-map-mask gpio-map-pass-thru gpio-map timer-name timer-freq timer-num #clock-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,remote-resource-name qcom,units qcom,lpr-enable protocol-name protocol-idx worker-type worker-priority num-signals client-mapping qcom,offset qcom,client qcom,out-mask clock-names clocks qup_id qup_common_offset se_wrapper_base_offset core_frequency qup_flags num_se icb_master_qup_core icb_slave_qup_core icb_qup_ddr_master icb_qup_ddr_slave icb_cpu_master_proc icb_cpu_qup_slave core_offset se_flags se_index FIFO_MODE protocol_supported interface_supported gpii_list num_gpiis ring_size_multiplier core_irq pdc_irq parent_wakeup_gpio i2c_hub shared_se dfs_enable pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 current-speed pinctrl-6 pinctrl-7 supported_hdr label assigned-address auto-suspend-delay-ms num_top_qups irq_num qup0_cfg gsi_pa tcsr_addr tcsr_gpii_offset tcsr_irq gpii_interrupts num_gpii active is_common_irq zephyr,sram zephyr,console regulators xob-clock cxo-stub diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per proc-name chip-info uart1 i2c7 i3c6