ELF 4 4 C C ` 8 8
C 8 # ( " ! sifive,e61,kaanapali_soccp_board
&SiFive E6 cpus cpu@0 sifive,e66 ,cpu 8
top_qup2_se4_i3c_sleep
= ! > ! top_qup2_se4_i2c_active
=
>
top_qup2_se4_i2c_sleep
= > top_qup2_se4_spi_active
=X >X ?X @X top_qup2_se4_spi_sleep
= ! > ! ? ! @ ! top_qup2_se4_uart_active
= > ? @ top_qup2_se4_uart_sleep
= > ? @ top_qup3_se0_i3c_active
A
B
top_qup3_se0_i3c_sleep
A ! B ! top_qup3_se0_i2c_active
A
B
top_qup3_se0_i2c_sleep
A B top_qup3_se0_spi_active
AX BX CX DX top_qup3_se0_spi_sleep
A ! B ! C ! D ! top_qup3_se0_uart_active
A B C D top_qup3_se0_uart_sleep
A B C D top_qup3_se1_i3c_active
E
F
top_qup3_se1_i3c_sleep
E ! F ! top_qup3_se1_i3c_ibi_active
G
H
top_qup3_se1_i3c_ibi_sleep
G ! H ! top_qup3_se1_i2c_active
E
F
top_qup3_se1_i2c_sleep
E F top_qup3_se1_spi_active
EX FX IX JX top_qup3_se1_spi_sleep
E ! F ! I ! J ! top_qup3_se1_uart_active
E F I J top_qup3_se1_uart_sleep
E F I J top_qup3_se2_i3c_active
K
L
top_qup3_se2_i3c_sleep
K ! L ! top_qup3_se2_i3c_ibi_active
M
N
top_qup3_se2_i3c_ibi_sleep
M ! N ! top_qup3_se2_i2c_active
K
L
top_qup3_se2_i2c_sleep
K L top_qup3_se2_spi_active
KX LX OX PX top_qup3_se2_spi_sleep
K ! L ! O ! P ! top_qup3_se2_uart_active
K L O P top_qup3_se2_uart_sleep
K L O P top_qup3_se3_i3c_active
Q
R
top_qup3_se3_i3c_sleep
Q ! R ! top_qup3_se3_i2c_active
Q
R
top_qup3_se3_i2c_sleep
Q R top_qup3_se3_spi_active
QX RX SX TX top_qup3_se3_spi_sleep
Q ! R ! S ! T ! top_qup3_se3_uart_active
Q R S T top_qup3_se3_uart_sleep
Q R S T top_qup3_se4_i3c_active
U
V
top_qup3_se4_i3c_sleep
U ! V ! top_qup3_se4_i2c_active
U
V
top_qup3_se4_i2c_sleep
U V top_qup3_se4_spi_active
UX VX WX XX top_qup3_se4_spi_sleep
U ! V ! W ! X ! top_qup3_se4_uart_active
U V W X top_qup3_se4_uart_sleep
U V W X top_qup3_se5_i3c_active
Y
Z
top_qup3_se5_i3c_sleep
Y ! Z ! top_qup3_se5_i2c_active
Y
Z
top_qup3_se5_i2c_sleep
Y Z
top_qup3_se5_spi_active
YX ZX [X \X top_qup3_se5_spi_sleep
Y ! Z ! [ ! \ ! top_qup3_se5_uart_active
Y Z [ \
top_qup3_se5_uart_sleep
Y Z [ \ top_qup4_se0_i3c_active
]
^
top_qup4_se0_i3c_sleep
] ! ^ ! top_qup4_se0_i3c_ibi_active
_
`
top_qup4_se0_i3c_ibi_sleep
_ ! ` ! top_qup4_se0_i2c_active
]
^
top_qup4_se0_i2c_sleep
] ^ top_qup4_se0_spi_active
]X ^X aX bX top_qup4_se0_spi_sleep
] ! ^ ! a ! b ! top_qup4_se0_uart_active
] ^ a b top_qup4_se0_uart_sleep
] ^ a b top_qup4_se1_i3c_active
c
d
top_qup4_se1_i3c_sleep
c ! d ! top_qup4_se1_i3c_ibi_active
e
f
top_qup4_se1_i3c_ibi_sleep
e ! f ! top_qup4_se1_i2c_active
c
d
top_qup4_se1_i2c_sleep
c d top_qup4_se1_spi_active
cX dX gX hX top_qup4_se1_spi_sleep
c ! d ! g ! h ! top_qup4_se1_uart_active
c d g h top_qup4_se1_uart_sleep
c d g h top_qup4_se2_i3c_active
i
j
top_qup4_se2_i3c_sleep
i ! j ! top_qup4_se2_i3c_ibi_active
k
l
' top_qup4_se2_i3c_ibi_sleep
k ! l ! ( top_qup4_se2_i2c_active
i
j
! top_qup4_se2_i2c_sleep
i j " top_qup4_se2_spi_active
iX jX mX nX # top_qup4_se2_spi_sleep
i ! j ! m ! n ! $ top_qup4_se2_uart_active
i j m n % top_qup4_se2_uart_sleep
i j m n & top_qup4_se3_i3c_active
o
p
/ top_qup4_se3_i3c_sleep
o ! p ! 0 top_qup4_se3_i2c_active
o
p
) top_qup4_se3_i2c_sleep
o p * top_qup4_se3_spi_active
oX pX qX rX + top_qup4_se3_spi_sleep
o ! p ! q ! r ! , top_qup4_se3_uart_active
o p q r - top_qup4_se3_uart_sleep
o p q r . top_qup4_se4_i3c_active
s
t
7 top_qup4_se4_i3c_sleep
s ! t ! 8 top_qup4_se4_i2c_active
s
t
1 top_qup4_se4_i2c_sleep
s t 2 top_qup4_se4_spi_active
sX tX uX vX 3 top_qup4_se4_spi_sleep
s ! t ! u ! v ! 4 top_qup4_se4_uart_active
s t u v 5 top_qup4_se4_uart_sleep
s t u v 6 ibi_i3c_qup1_se4_scl % ibi_i3c_qup1_se4_sda $ ibi_i3c_qup1_se7_scl = & ibi_i3c_qup1_se7_sda < % ibi_i3c_qup2_se0_scl , ibi_i3c_qup2_se0_sda + ibi_i3c_qup2_se1_scl 2 ibi_i3c_qup2_se1_sda 1 ibi_i3c_qup3_se1_scl H ibi_i3c_qup3_se1_sda G ibi_i3c_qup3_se2_scl
N ibi_i3c_qup3_se2_sda M ibi_i3c_qup4_se0_scl 1 ` ibi_i3c_qup4_se0_sda 0 _ ibi_i3c_qup4_se1_scl f ibi_i3c_qup4_se1_sda e ibi_i3c_qup4_se2_scl ! l ibi_i3c_qup4_se2_sda k qup1_se0_l0 P qup1_se0_l1 S qup1_se0_l2 R qup1_se0_l3 Q qup1_se1_l0 J qup1_se1_l1 K
qup1_se1_l2 L qup1_se1_l3 M qup1_se2_l0 (
qup1_se2_l1 ) qup1_se2_l2 * qup1_se2_l3 + qup1_se3_l0 , qup1_se3_l1 - qup1_se3_l2 . qup1_se3_l3 / qup1_se4_l0 $ qup1_se4_l1 % qup1_se4_l2 & qup1_se4_l3 ' qup1_se5_l0 4 qup1_se5_l1 5 qup1_se5_l2 6 qup1_se5_l3 7 qup1_se6_l0 8 qup1_se6_l1 9 qup1_se6_l2 : ! qup1_se6_l3 ; " qup1_se7_l0 < # qup1_se7_l1 = $ qup1_se7_l2 > ' qup1_se7_l3 ? ( qup2_se0_l0 ) qup2_se0_l1 * qup2_se0_l2 - qup2_se0_l3 . qup2_se1_l0 / qup2_se1_l1 0 qup2_se1_l2 3 qup2_se1_l3 4 qup2_se2_l0 u 5 qup2_se2_l1 v 6 qup2_se2_l2 w 7 qup2_se2_l3 x 8 qup2_se3_l0 z 9 qup2_se3_l1 { : qup2_se3_l2 | ; qup2_se3_l3 } < qup2_se4_l0 = qup2_se4_l1 > qup2_se4_l2 ? qup2_se4_l3 @ qup3_se0_l0 @ A qup3_se0_l1 A B qup3_se0_l2 @ C qup3_se0_l3 A D qup3_se1_l0 E qup3_se1_l1 F qup3_se1_l2
I qup3_se1_l3 J qup3_se2_l0 K qup3_se2_l1
L qup3_se2_l2 O qup3_se2_l3 P qup3_se3_l0 Q qup3_se3_l1 R qup3_se3_l2 S qup3_se3_l3 T qup3_se4_l0 U qup3_se4_l1 V qup3_se4_l2 W qup3_se4_l3 X qup3_se5_l0 Y qup3_se5_l1 Z qup3_se5_l2 [ qup3_se5_l3 \ qup4_se0_l0 0 ] qup4_se0_l1 1 ^ qup4_se0_l2 2 a qup4_se0_l3 3 b qup4_se1_l0 c qup4_se1_l1 d qup4_se1_l2 g qup4_se1_l3 h qup4_se2_l0 i qup4_se2_l1 ! j qup4_se2_l2 " m qup4_se2_l3 # n qup4_se3_l0 y o qup4_se3_l1 T p qup4_se3_l2 y q qup4_se3_l3 T r qup4_se4_l0 s qup4_se4_l1 t qup4_se4_l2 u qup4_se4_l3 v vcs qcom,vcs icbarb qcom,icbarb spmi-bus@4c400000 ) qcom,spmi-pmic-arb qcom,spmi-pmic-arb-v8 8L@ ' + . 7 pmic@0 qcom,spmi-pmic 8 rtc@6100 qcom,pmic-rtc 8 a spmi-vadc@9400 qcom,spmi-vadc 8 G U Y ] ' b w vadc_ch_cfg VPH_PWR lVPH_PWR r x W ' VBATT lVBATT r x W ' VBATT_2S lVBATT_2S r x W ' VBATT_2S_MID
lVBATT_2S_MID r x W ' CHG_TEMP lCHG_TEMP r x W ' BATT_THERM lBATT_THERM r D x W ' BATT_THERM_PU_10K lBATT_THERM_PU_10K r $ x W ' ' BATT_THERM_PU_400K lBATT_THERM_PU_400K r d x W ' BATT_ID_OHMS
lBATT_ID_OHMS r E x W ' BATT_ID_OHMS_PU_10K lBATT_ID_OHMS_PU_10K r % x W ' ' BATT_ID_OHMS_PU_400K lBATT_ID_OHMS_PU_400K r e x W ' CONN_THERM_PM_07 lCONN_THERM_PM_07 r G x W ' USB_SNS_V_MV
lUSB_SNS_V_MV r x W ' USB_IN_I_MA_PM_07 lUSB_IN_I_MA_PM_07 r x W ' VIN_MUX lVIN_MUX r x W ' IBATT_MA lIBATT_MA r x W ' IBATT2_MA
lIBATT2_MA r x W ' BATT2_THERM lBATT2_THERM r L x W ' BATT2_THERM_PU_10K lBATT2_THERM_PU_10K r , x W ' ' BATT2_THERM_PU_400K lBATT2_THERM_PU_400K r l x W ' BATT2_ID_OHMS lBATT2_ID_OHMS r K x W ' BATT2_ID_OHMS_PU_10K lBATT2_ID_OHMS_PU_10K r + x W ' ' BATT2_ID_OHMS_PU_400K lBATT2_ID_OHMS_PU_400K r k x W ' USBC_MUX_OPEN lUSBC_MUX_OPEN r x W ' USBC_MUX_10K
lUSBC_MUX_10K r 3 x W ' ' USBC_MUX_100K lUSBC_MUX_100K r S x W ' USBC_MUX_400K lUSBC_MUX_400K r s x W ' WLS_THERM
lWLS_THERM r M x W ' ICHG_SMB_SMB_A lICHG_SMB_SMB_A r x ( ) W ' ICHG_SMB_SMB_B lICHG_SMB_SMB_B r x ( ) W ' IIN_SMB_SMB_A lIIN_SMB_SMB_A r x ( ) W ' IIN_SMB_SMB_B lIIN_SMB_SMB_B r x ( ) W ' SMB_TEMP_I_SMB_A lSMB_TEMP_I_SMB_A r x W ' SMB_TEMP_I_SMB_B lSMB_TEMP_I_SMB_B r x W ' vadc-avg-ch gpio-map pmic@1 qcom,spmi-pmic 8 pinctrl@8800 qcom,pmic-gpio 8 spmi-bus@4c425000 ) qcom,spmi-pmic-arb qcom,spmi-pmic-arb-v8 8L@ ' + . 7 watchdog qcom,hwdog TOP_QUP_1@a00000 qcom,qup-v2-controller 8 core2x core s-ahb m-ahb xۂ x@ x4(~ xQ'b
# * > 8 Q ) d v Y ' Fok TOP_QUP_1_SE_0 qcom,se-v2-controller 0
! * 2 E M se-clk x > Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e y o z y { | } ~ Fdisabled TOP_QUP_1_SE_1 qcom,se-v2-controller @ 0 ! * 2 E M se-clk xދڬ Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_1_SE_2 qcom,se-v2-controller 0
! * 2 E M se-clk xE4 Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_1_SE_3
qcom,qup-i2c 0
! * 2 E M se-clk xl Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fokay smb0@68 qcom,pm-battman-i2c 8 h smb1@69 qcom,pm-battman-i2c 8 i smb2@6A qcom,pm-battman-i2c 8 j wls_chip_cfg@30 qcom,pm-battman-i2c 8 0 TOP_QUP_1_SE_4 qcom,se-v2-controller 0
! * 2 E M se-clk x*KF Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_1_SE_5
qcom,qup-i2c @ 0 ! * 2 E M se-clk xy Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fokay smb3@34 qcom,pm-battman-i2c 8 4 smb4@35 qcom,pm-battman-i2c 8 5 TOP_QUP_1_SE_6
qcom,qup-i2c 0
! * 2 E M se-clk xo&j Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_1_SE_7 qcom,se-v2-controller 0 ! * 2 E M se-clk xG5 Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_2@840000 qcom,qup-v2-controller 8 core2x core s-ahb m-ahb xpi x_h x0nU x~t
# * > 9 Q ' d v Y % Fok TOP_QUP_2_SE_0 qcom,se-v2-controller 0 ! * 2 E M se-clk xb8 b Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c_ibi-default i3c_ibi-sleep e o y Fokay TOP_QUP_2_SE_1 qcom,se-v2-controller @ 0 ! * 2 E M se-clk x' Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_2_SE_2 qcom,qup-uart 0 ! * 2 E M se-clk x+ Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fokay - TOP_QUP_2_SE_3 qcom,se-v2-controller 0 ! * 2 E M se-clk x,y Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_2_SE_4 qcom,se-v2-controller 0 ! * 2 E M se-clk xy~ Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_3@1900000 qcom,qup-v2-controller 8 core2x core s-ahb m-ahb xe x J x7i x6<
# * # > Q d v Y Fdisabled TOP_QUP_3_SE_0 qcom,se-v2-controller 0 ! * 2 E M se-clk x= Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_3_SE_1 qcom,se-v2-controller @ 0 ! * 2 E M se-clk xB Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_3_SE_2 qcom,se-v2-controller 0 ! * 2 E M se-clk x+ o Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_3_SE_3 qcom,se-v2-controller 0 ! * 2 E M se-clk xoP Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_3_SE_4 qcom,se-v2-controller 0 ! * 2 E M se-clk xd Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_3_SE_5 qcom,se-v2-controller @ 0 ! * 2 E M se-clk x Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o
y
Fdisabled TOP_QUP_4@1a00000 qcom,qup-v2-controller 8 core2x core s-ahb m-ahb x- xz x y xP풧
# *
> Q d v Y Fdisabled TOP_QUP_4_SE_0 qcom,se-v2-controller 0 ! * 2 E M se-clk x n Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e o y Fdisabled TOP_QUP_4_SE_1
qcom,qup-i3c @ 0 ! * 2 E M se-clk x6VF b Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c_ibi-default i3c_ibi-sleep e o y Fdisabled i3c_dev0@6A000002080070120B qcom,qup-i3c-dev 8 j p Fdisabled TOP_QUP_4_SE_2 qcom,se-v2-controller 0 ! * 2 E M se-clk x; b Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c_ibi-default i3c_ibi-sleep e ! o " y # $ % & ' ( Fokay TOP_QUP_4_SE_3 qcom,se-v2-controller 0 ! * 2 E M se-clk xk Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e ) o * y + , - . / 0 Fdisabled TOP_QUP_4_SE_4 qcom,se-v2-controller 0 ! * 2 E M se-clk xx{; Z Wi2c-default i2c-sleep spi-default spi-sleep uart-default uart-sleep i3c-default i3c-sleep e 1 o 2 y 3 4 5 6 7 8 Fdisabled ibi_top_0_cfg@EC90000 qcom,ibi-controller 8
# + Fok ibi_top_1_cfg@ECA0000 qcom,ibi-controller 8
# + Fok ibi_top_2_cfg@ECB0000 qcom,ibi-controller 8
# + Fok ibi_top_3_cfg@ECC0000 qcom,ibi-controller 8
# + Fok ibi_top_4_cfg@ECD0000 qcom,ibi-controller 8
# + Fok ibi_top_5_cfg@ECE0000 qcom,ibi-controller 8
# + Fok ibi_top_6_cfg@ECF0000 qcom,ibi-controller 8
# + Fok ibi_top_7_cfg@ED00000 qcom,ibi-controller 8
# + Fok ibi_top_8_cfg@ED10000 qcom,ibi-controller 8
# + Fok qup_tcsr_info qcom,quptcsr-controller 7 tcsr_cfg0 T D Mp Vp _p hp gsi_info qcom,gsi-controller gsi_qup_0 q x * @ 3 gsi_qup_1 q @ xp * @ 3 gsi_qup_2 q @ xp * @ 3 gsi_qup_3 q@ xp * @ 3 gsi_qup_4 q@ xp * @ 3 qntm_proc_config qcom,qntm-proc-config soccp [SOCCP] qntm:soccp qntm_apss_glink_config qcom,qntm-apss-glink-config soccp_uefi minidump qcom,minidump
SOCCP_PIL md-region-list SOCCP-DLS
SOCCP_DLS # SOCCP-DBG
SOCCP_DBG # msm_fence_shm@d4e23000 qcom,msm-fence-shm 80 - msm_fence_ctl qcom,msm-fence-ctl )/core/cpu/vdd 4AA =," G P @ msm_fence_add_clients qcom,msm-fence-add-clients a f k o memory@d7a00000 8נ 9 synx-hw-mutex@1f4a000 8 : global-hw-mutex@1f4b000 8 ; ipclite
qcom,ipclite t 9 { : ; battman_gpio qcom,pm-battman-msm-gpio < : @ < D @ < 9 @ < E @ chosen /soc/dtim@A03D0000 % /soc/TOP_QUP_2@840000/TOP_QUP_2_SE_2 board-id default
sw diag
qcom,diag diagcfg_cmd
"0
=
X.
l.
.
.
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.
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. %. E. ^. r. . . . .! .# .$ .% 5.& R.' g.( y.) diagcfg_param @
0
I
h
2
% = @ T m < % @ ] x K , K a z 5 Q h @ < pmic-sw therm-table w therm_tb1 @x - $ R Ȩ (l m % 1 z % * 5` / 4 9 > C i H V M G| R ;` W 18 \ )h a " f L k p " u z
\
therm_tb2 X $ @ 8 ( ѐ H jL *h x 4 ƨ
0
` b \ ( MH vadc_ibatt_tb N N usbin_i_tb S chg_temp_tb ŀ S p smb_itemp_tb $ S + smb_vtemp_tb S I ichg_fb_tb 9 S - prm qcom,pmic-prm prm-rsrcs qcom,prm-rsrcs prm-regulator-b1b-e0 qcom,prm-regulator B1B_E0 prm-regulator-b2b-e0 qcom,prm-regulator B2B_E0 @ prm-regulator-l5b-e0 qcom,prm-regulator L5B_E0 = prm-regulator-l15b-e0 qcom,prm-regulator L15B_E0 > prm-regulator-l1d-e0 qcom,prm-regulator L1D_E0 ? prm-regulator-l3d-e0 qcom,prm-regulator L3D_E0 prm-regulator-l4f-e0 qcom,prm-regulator L4F_E0 prm-pam
qcom,prm-pam usb-hs0 usb_hs0 usb-hs0-l5b-e0 / = $ : usb-hs0-l15b-e0 / > $ : usb-hs0-l1d-e0 / ? $ : usb-pd-phy usb_pd_phy0 usb-pd-phy-l5b-e0 / = $ : vconn-bob2 vconn_bob2 vconn-bob2-b2b-e0 / @ $ :
arc-cxo qcom,prm-rpmh-xo Dxo ' core pmic battman platform_cfg qcom,pm-battman-plat W b j ' w h u0 w !2 1 @ Q b u d beh_cfg qcom,pm-battman-plat-beh-cfg 2 D chg_table_cfg # qcom,pm-battman-plat-chg-table-cfg R 6 ^ : " m LK@ { esd_cfg qcom,pm-battman-plat-esd-cfg
batt_auth_cfg # qcom,pm-battman-plat-batt-auth-cfg . J c { +&D;^@?c8Jb low_batt_shutdown_cfg + qcom,pm-battman-plat-low-batt-shutdown-cfg < power_ok_boot_criterion - qcom,pm-battman-plat-power-ok-boot-criterion %
H < [ gauge_cfg qcom,pm-battman-gauge w
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& charger_cfg qcom,pm-battman-charger jeita_cfg " qcom,pm-battman-charger-jeita-cfg : D R g 7 7 { F F therm_thresh_cfg ) qcom,pm-battman-charger-therm-thresh-cfg d < P F < 2 7 mtc_chg_cfg $ qcom,pm-battman-charger-mtc-chg-cfg 0 , < P 2 d d q 2 wls_chg_cfg $ qcom,pm-battman-charger-wls-chg-cfg
chg_det_cfg $ qcom,pm-battman-charger-chg-det-cfg # chg_icm_cfg $ qcom,pm-battman-charger-chg-icm-cfg 1 > ufcs_cfg ! qcom,pm-battman-charger-ufcs-cfg I P [ d : ; r N d d G batt_health_cfg ( qcom,pm-battman-charger-batt-health-cfg P F usbpd_cfg qcom,pm-battman-usbpd ucsi_cap_cfg # qcom,pm-battman-usbpd-ucsi-cap-cfg 2 @F = F S Z a 0 ucsi_conn_cap_cfg ( qcom,pm-battman-usbpd-ucsi-conn-cap-cfg k s | lpm_cfg qcom,pm-battman-usbpd-lpm-cfg pd_policies_cfg & qcom,pm-battman-usbpd-pd-policies-cfg 2 &&, ,!d 4 S G Z k zÀ rp À 6, ' > QÀ a j n ~ 2 pd_static_info_cfg ) qcom,pm-battman-usbpd-pd-static-info-cfg lpd_cfg qcom,pm-battman-usbpd-lpd-cfg % < 5 K ] tcpc_cfg qcom,pm-battman-usbpd-tcpc-cfg m w # 5 C cid_cfg qcom,pm-battman-usbpd-cid-cfg K R \ q vdm_cfg qcom,pm-battman-usbpd-vdm-cfg @ C e psm_cfg qcom,pm-battman-usbpd-psm-cfg " rpm_cfg qcom,pm-battman-usbpd-rpm-cfg 9 I \ a o b pmi_cfg qcom,pm-battman-pmi pmic0 qcom,pm-battman-spmi smb_cfg_1s qcom,pm-battman-smb smb_cfg_2s qcom,pm-battman-smb smb5 qcom,pm-battman-spmi
aliases % /soc/TOP_QUP_1@a00000/TOP_QUP_1_SE_3 % /soc/TOP_QUP_1@a00000/TOP_QUP_1_SE_5 % /soc/TOP_QUP_1@a00000/TOP_QUP_1_SE_6 % /soc/TOP_QUP_2@840000/TOP_QUP_2_SE_2 #address-cells #size-cells compatible model device_type reg riscv,isa status cpu-power-states #interrupt-cells interrupt-controller phandle power-state-name substate-id min-residency-us exit-latency-us interrupts-extended reg-names riscv,max-priority riscv,ndev interrupt-parent interrupts zephyr,memory-region irq-conditioning-base plic-mask-offset plic-type-offset plic-clr-offset clint-mask-offset clint-type-offset clint-clr-offset nmi-addr nops-pre-cflush nops-post-cflush dump-addr dtb-address-offset aop_info_msg_ram_proc_view_addr num_drvs drv0_drv_id drv0_hw_drv drv0_global_drv drv0_in_irq_num drv0_in_irq_level drv0_epcb_timeout_irq_num drv0_epcb_timeout_irq_level drv0_num_tcs drv0_num_cmds drv0_hwio_base drv0_tcs_map drv0_num_amcs drv0_sleep_start drv0_wake_start host remote-host fifo-size mtu-size irq-out qos-max-rate local-host master-host channel-name transport host-name remote-ss ch-name options stack-size intents version-info-offset tcsr-base mutex-offsets-data wonce-offsets host-id fflags max-entries dest proc irq service_id instance_id #clock-cells protocol-name protocol-idx worker-type worker-priority #signals client-mapping timer-name timer-freq timer-num ngpios width version interrupt-names summary-targetproc summary-edgetriggered gpio-controller #gpio-cells configs mux #config-cells bid ee channels pdc-intc-parent use-interrupt sid mid pmic therm-tbl label hw-ch hw-settle avg-sp dec-ratio cal-method scaling scale-fcn pull-up asid int-table clock-names clocks qup_id qup_common_offset se_wrapper_base_offset core_frequency qup_flags num_se icb_master_qup_core icb_slave_qup_core icb_qup_ddr_master icb_qup_ddr_slave icb_cpu_master_proc icb_cpu_qup_slave core_offset ibi_instance se_flags se_index FIFO_MODE protocol_supported interface_supported gpii_list num_gpiis ring_size_multiplier core_irq pdc_irq parent_wakeup_gpio i2c_hub shared_se pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 auto-suspend-delay-ms bus-freq current-speed supported_hdr assigned-address ibi_id gpii gpii_irq gpii_pdc_irq mgr_irq mgr_pdc_irq num_top_qups qup0_cfg qup1_cfg qup2_cfg qup3_cfg qup4_cfg gsi_pa tcsr_addr tcsr_gpii_offset tcsr_irq gpii_interrupts num_gpii active is_common_irq proc_printsig proc_logsig proc_enum channel_name md-ss-id smem-entry-num pil-region-name is-pa clock-node ipcc-reg qtime-reg ipcc-ver excl-handler-reg dpu0 icp0 vpu ife0 memory synx-hw-mutex global-hw-mutex ufcs-dp-gpios smb-int-gpios wls-chip-ping-det-gpios wls-chip-int-gpios zephyr,sram zephyr,console proc-name chip-info diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per arr_id qcom,prm-vreg qcom,prm-control qcom,prm-type qcom,pm-index qcom,pm-sid qcom,pm-bid pam-name pam-mode-count pam-supply pam-modes clock-output-names struct-ver plat-id cpu-freq-khz ddr-freq-khz is-test-mode test-mode-flag chg-heartbeat-timer-ms dischg-heartbeat-timer-ms poll-timer-ms chg-done-timer-ms vbatt-avg-sample-size en-linear-soc soc-conv-pt notify-hlos-thr min-linear-soc wd-bark-timer-ms wd-bite-timer-ms gen-test-interface en-stepchg-jeita gnd-setting iterm-ma bmd-src-sel cable-state-check-timer-ms delta-batt-ov en-beh beh-debug-board beh-normal-batt beh-smart-auth-state beh-unknown-state beh-batt-miss-state beh-invalid-state beh-afp-state dbg-rid-cfg normal-rid-cfg smart-rid-cfg chg-table-max esd-timer-ms esd-voltage-mv esd-voltage-2s-mv esd-voltage-mv-sianode esd-voltage-2s-mv-sianode esd-init-soc en-batt-auth batt-auth-timeout-s batt-auth-checktimer-ms batt-unauth-charging-action batt-auth-public-key-len batt-auth-challenge-len batt-auth-response-len batt-auth-public-key en-batt-auth-bsi-chip low-batt-shutdown-feature-en low-batt-soc-thr critical-batt-soc-thr wdog-bite-timer-s en-soc-based-boot boot-to-hlos-thresh-mv boot-to-hlos-thresh-mv-sianode boot-to-hlos-thresh-soc-pct fg-selection vph-min-mv fvss-entry-delta-mv fvss-vbatt-filt-tau-us fcss-entry-delta-ma fcss-ibatt-filt-tau-us hold-soc-1-pct cl-learn-min-delta-soc cl-wt-learn soh-tbat-range-degc soh-soc-range ignore-shdn-soc-param pon-debug-fifo-count hpm-fifo-len vbatt-empty-1s vbatt-empty-2s vbatt-empty-1s-sianode vbatt-empty-2s-sianode en-split-profile seperate-2p-batt vbat-cut-off-mv vbat-cut-off-mv-sianode ibatt-cutoff-min-ma rconn-mohm ibatt-full-delta-ma jeita-alg afp-cold-degc jeita-hard-cold-degc jeita-hard-hot-degc jeita-hard-hys-degc afp-hot-degc vflt-nominal-mv fcc-nominal-ma die-shdn-temp-cfg die-rst-temp-cfg die-temp-cfg conn-shdn-temp-cfg conn-rst-temp-cfg conn-temp-cfg en-aged-batt-comp rechg-iterm rechg-soc-delta-pct rechg-delta-vflt-mv vflt-comp-mv iterm-comp-ma en-wls wls-pre-regulator boost-src otg-boost-src wls-tx-cfg ext-gpio-boost usb-switch wls-load-switch en-apsd-pwr qc-det-cfg dam-hc-override apsd-rerun-cfg en-ufcs en-dam-qc-usb force-eoc-5v ptm-cfg-1s se-idx se-int-num se-flags tlmm-gpio-num pmic-gpio-num pmic-idx ufcs-flags snk-max-mv snk-max-ma vdm-limit-cfg wd-timer-cfg-ms wd-timer-pet-ms hw-version sw-version prot-version en-chg-lmt charge-end-threshold charge-start-threshold attributes conn-num num-alt-mode bc-ver pd-ver typec-ver op-mode provider consumer dfp-swap-en ufp-swap-en src-swap-en snk-swap-en port-idx en-pd en-pan en-legacy-cable-det detach-holdoff-ms pan-version-max vconn-require-ra pd-rev snk-cap-size snk-caps-pdos snk-max-voltage-mv snk-max-current-ma snk-pwr-eval-alg snk-max-pwr-uw snk-op-pwr-uw snk-min-pwr-uw src-max-voltage-mv src-max-current-ma src-max-pwr-uw src-min-pwr-uw sys-power-budget src-cap-size src-caps-pdos en-pps en-vconn-swap en-fr-swap en-vdm-cable-discovery en-enterprise-mgmt slow-charge-thr mismatch-thr drp-pps-support mpm-snk-time-ms mpm-src-time-ms pan-ack-tmout-ms en-alt-modes-uefi en-alt-modes-hlos batt-cap-vid batt-pid src-cap-ext-cfg en-lpd en-fod rsbu-thr-kohm holdoff-time-ms cooldown-time-s mitigation-current-ma sink-periodic-lpd ccsts-based-fod en-trysnk en-trysrc dam-en dam-pmic-idx dam-pmic-gpio-num en-dam-src src-rp-val en-audio-adap usb-switch-notify-en vbus-timer-en vconn-timer-en vbus-rampdown-wait-ms vbus-default-mv vbus-init-step-mv vconn-src-sel frs-src en-cid pulse-sel cid-typec-attach-chk cid-lpd-timer-ms id-header-vdo cert-stat-vdo product-vdo dfp-product-vdo ufp-product-vdo resp-disc-sop power-key-timeout-ms power-state-to-led en-restart-flag en-ext-alert-type en-ext-alert-type-uefi rpm_access_mode rpm_intrx_gpio_cfg rpm_intrx_gpio_idx rpm_inttx_gpio_cfg rpm_inttx_gpio_idx plat-type bus-id sid-id i2c3 i2c5 i2c6 uart10 h
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