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T_pcie postlinkup failed Exit: XMLH_LINK_UP pcie linkup failed Exit pcie_osal_memcpy failed! pcie_get_msi_config: %x, %x, %x, %x, %x, %x, %x, %x Establish PCIe link Waiting for the PCIe link to enumerate Enumeration did not happen within timeout PCIe link enumerated Exiting Attestation mode. Remapping BAR4/5 Change Device state to : %d atu_array is NULL or entry_count = %d > 2 Unhandled conditions host_ctrl_addr.pa_low=0x%x host_ctrl_addr.pa_hi=0x%x host_data_addr.pa_low=0x%x host_data_addr.pa_hi=0x%x Unhandled conditions host_ctrl_addr.pa_low=0x%x host_ctrl_addr.pa_hi=0x%x host_data_addr.pa_low=0x%x host_data_addr.pa_hi=0x%x PCIE_PCIE_INT_ALL_STATUS= %x Couldn't malloc memregion for pcie_ctx MHI data region overlap with MHI control region p O{C hZN 5 k 2iZ{AO¨_O{C C s>D @ q@ j ˪ C {AO¨_9*=D s h@ 4՛Rh k
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Kr 2 *H H NGh@ )B) 2 )NG*@_ T))@?A T )BN *!p 2A d q T ٝ 2 q T%#NGA *{AO¨_ _Rr@ q_֨ :9_֨ z9_PERST pin is HIGH pcie_phy_init failed Starting enumeration PCIE_LINKSTATUS_ENUMERATED %s: Failed to read variable pcie_bar3_mode pcie_i_set_default_bar4_5_addr pcie_bar3_mode stored in flash is %u PCIE BAR4/5 addr: 0x%llx PCIe DMA init failed Link not in L1ss *_WO{ C ѵ >D @ 58R rCR*5
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*.26:>RZ^J h ? ) ! aT{AO¨_8R%r2 _bhi_reset mhi sys error: true mhi sys error: false { V d'S *{_____WO{ ):3@h@ 44@ * 2
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`3 2 3 2] {BOAWè_6*O{C p2s 3 4 2l 2 *{AO¨_BAR4 size is not 2GB. Attestation is not allowed Attestation CMD %d received. Entering Attestation mode Error while reading flash Opening flash for attestation 0:ALL Error while opening flash partition Error with 0 byte flash size. Closing flash partition Error while closing flash partition Couldn't get DDR size. Requested DDR block is out of range. Mapping DDR block %d to BAR4/5 O{C A5 q T 2 A;9 B=D {A!O¨@ ֔ ЊF{9 6{AO¨_֓ sb;@Rr2 5h@ * @i@ ? 4 =D{AO¨` ֩ x!=D{AO¨ ֍ mG!:B;@%@@? 4 =D{AO¨ = * R, 2F;9V %>D{A "!BO¨ O{C Д2? @RJA9s;r`2
h JA9i 9{AO¨__WO{ ѵ * >D
R# *w # , 4i Q( @ T_ + T @8 8 ?3kaT # )#@9 Rr 2 q T# * q\ * {COBWA_Ĩ_)O{C mG (E{9 q T i{9I 7 JA{9 7 @ 2h)@l;9 ?;9{AO¨_O{C `nG E{9? q! T @)@ E;9 ? 4 H D! RR ? `nG` 4 j D RR@? {AO¨_%s: Skipped because Auto SKU. bmc_command_parser_init [I2CS]: Attach Failed [I2CS]: Open Failed [I2CS]: Set Callback Failed bmc_message_parser.c O{C C ѳ s>D 9 42 9 ̬Řr
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9 9 9 @ * * 2, q T q Tn!O
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* {BOAWè_S%FRU: Received FRU data version is %d Failed to read PVS upper threshold variable for SKU %d critical_threshold_config critical_threshold_config_pcie Failed to read PVS critical threshold variable for SKU %d tdp_config_interfaces Failed to read PVS tdp_config_interfaces variable tdp_config Failed to read PVS tdp_config variable Failed to get historical max asic temperature. Invalid TDP write permit. Error setting TDP permit = %d TDP configuration not permitted over BMC - tdp_write_permit = %d Invalid TDP write request. Requested %d Watts. Error setting tdp_config variable %d Error setting lower threshold = %d for SKU = %d Error setting upper threshold = %d for SKU = %d ras_ecc_enable_config Failed to read PVS ras_ecc_enable_config variable %s: Unsuccessful PVS read for pvs_control_config, %d bmc_get_pvs_control_config_status %s: given value is not supported %d %s: Unsuccessful PVS write for pvs_control_config, %d %s: Unsuccessful STICKY write for pvs_control_config, %d %s: Error: wrong input 1?+R R @9
@9 9 9 9
9 9 9_ q T 2) 9_ qh T 9_ 1 TR, 9_ 1c T( 9_O{C C ѓ * s>D * 9 ` 42 @9 qa T 2 T Q q ) 1l@i˩ C {AO¨_$O{C C ѓ 2 s>D * 9 ` 42 @9 qa T 2 T Q q ) 1l@i˩ C {AO¨_#O{C ` 4? 2 y ` 4? 2i y{AO¨_O{C s2? *`
2 2&'h@9)Rj@9 R 2 9i 9h
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2 2&@9)R@9 R@9R @9~S~S 9~S
9 9 9" 9& 9 9* 9 92 9. 96 9: 9J9@i {BOAWè_օ#_WO{ ѕ 2?>DSR *
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9 9 9 9D 0 ? @ >D \ ?lR" 95Q @#@9N 9& 9KH* 9LPMX2 9N`6 9Oh: 9Pp> 9QxB 9. 9F 9J 9J9@ {COBWA_Ĩ_7#_WO{ C є >D2? *
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9 9 9 9@ {COBWA_Ĩ_"g_WO{** E 3 2? *
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9 9 9 9R *( 4 )=D p!$* ?@9 2@9 9 9
9 9 {DOCWB_AgŨ_ֿ& q T@9 2@9 9 9
9 9 9 9 RR& 9* " 9" B( 2
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9j 9k 9 9l" 9& 9`* 92 9`. 96 9!> 9`: 9tJ9{AO¨_O{C s2? *`
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9}S 9 9" 9 9* 9& 9. 92 96 9J9@i {BOAWè_։!O{C 2?SR *
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9 9
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9 9 =D ?։@9+ R@9 9
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aQ_- q T k=iyj @8? ) kx aT =D !!! ? * 5Q? qH T A?yi@ * q` T q! T 2* * q T q T 9 9 9 9 9 9) q T) q T ? q! T@9j Q_ q T@9k qc T 'R>D@?)R @9 R 9!RCD ?R (`- &>D ? 2 * 4 q Tq Tq Tq Tq T2R R. 8 2 9
9 9 9 9
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d%=D* ? 2 9 2N9%s: DDR zero'ed out after ecc-init = %d bmc_handle_ipmi_vs_command_code_87 %s: Uptime = %d ms (0x%x) %s: DDR address 0x%08llx has value 0x%x bmc_handle_ipmi_vs_command_code_88 %s: DDR address is out of range %s: Variable: %s read failed with status =%d bmc_handle_ipmi_vs_command_code_89 %s: Variable: %s Write failed with status =%d bmc_handle_ipmi_vs_command_code_90 PVS corruption failed %s: dump size = 0x%x bmc_handle_ipmi_vs_command_code_198 %s: file offset = 0x%x, file length = 0x%x bmc_handle_ipmi_vs_command_code_205 %s: Get crash dump failed %d Incorrect msg length for command: 208, msg length: %d Requested Record Id 0x%x not found in Flash Failed to get SEL record IDs and count from flash. %s: Operation type= %d bmc_handle_ipmi_vs_command_code_207 %s: Opcode val = %d %s: Get CRC Opcode val = %d, partition_enum = %d %s: Get CRC val = %d %s: Unsupported Opcode val = %d %s: Size of image received= %d %s: Unsupported Operation type= %d No new records found in Flash SEL record read from Flash failed %s: DDR address given by user = 0x%08llx bmc_ipmi_vs_cmd_write_parser PVS variable name = %s %s: PVS variable name = %s data length= %d, data=%d [Attestation]Received I2C write command code offset %d Received I2C write request for non supported ipmi vs command code offset %d Received non supported command code offset %d Incompatible SKU type for command: 242 Invalid msg length for command: 242, msg length: %d Invalid base address and/or length for command: 242 CEC read register failed for command: 242 g_WO{ є i >D (AO9 4 ; 2Vy? ka T *yh@9 q Tj@9_q` TRk@9 qA T * 2 `3H=D ?\ 2k ki@waA
9J-RVy Hrj@9mch@9. Mb m 2~͛KR# y2@ @q}S+ 9r}S`}S1
92 9R 9 2/ 9# 9f@9? 9G 9g
@9K 9O 9a@9S 9W 9[ 9_ 9 Q % q T
!2yh@ '@yq >D 5!B" #}S ? 5 '@y@y H4=D ~S ?֏
'@y 6C>DA B|S` ?@G {DOCWB_AgŨ_ *[ 4\ [ 4\ 4\ 4\ 4\ 4\ [ T\ BMC SEL record creation failed due to NULL callback data. BMC SEL record 0x%x successfully created for Sensor type: 0x%x Sensor_num: 0x%x BMC SEL record creation failed due to %s. Sensor type: 0x%x Sensor_num: 0x%x BMC SEL record creation failed due to unknown error. Sensor type: 0x%x Sensor_num: 0x%x oO{ є >D!# 3" * 4 @)=D* ?& # 2 *x! *) 4 j>D *@?# K" h>D *+ 4 * ? # A" * 4 =D
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*C {AO¨_O{C C t 2 >D 2 9 *=D 4 ? @9 ?@ *C {AO¨_ERROR: CEC173x: I2C context is not initialized ERROR: CEC173x: invalid parameters for read request. Provided read length: %d ERROR: CEC173x: Invalid register read address (0x%02x) ERROR: CEC173x: Failed to read from device: 0x%02x, reg_addr: 0x%02x, result: 0x%x ERROR: CEC173x: invalid parameters for write request. Provided write length: %d ERROR: CEC173x: Invalid register write address (0x%02x) ERROR: CEC173x: Failed to write to device: 0x%02x, reg_addr: 0x%02x, data: 0x%02x, result: 0x%x ERROR: CEC173x: Context is already initialized ERROR: CEC173x: Failed to Attach ERROR: CEC173x: Failed to Open ERROR: CEC173x: Failed I2C reset ERROR: CEC173x: Failed to read register address: %02x ERROR: CEC173x: CEC in bypass:Failed to read AP_TABLE_STATUS0_R INFO: CEC173x:AP_TABLE_STATUS0_R 0x%02x ERROR: CEC173x: CEC in bypass:Failed to read AP_TABLE_STATUS1_R INFO: CEC173x:AP_TABLE_STATUS1_R 0x%02x ERROR: CEC173x: Failed to read MSB FW Build ID INFO: CEC173x:MSB FW Build ID 0x%02x ERROR: CEC173x: Failed to read LSB FW Build ID INFO: CEC173x:LSB FW Build ID 0x%02x ERROR: CEC173x: Failed to read FLASH_IMG_VLD_STS_AP1_R INFO: CEC173x:FLASH_IMG_VLD_STS_AP1_R 0x%02x%02x%02x%02x ERROR: CEC173x: Failed to read FLASH_IMG_VLD_STS_AP0_R INFO: CEC173x:FLASH_IMG_VLD_STS_AP0_R 0x%02x%02x%02x%02x ERROR: CEC173x: Failed to read FLASH_IMG_VLD_RTRY_STS_AP1_R INFO: CEC173x:FLASH_IMG_VLD_RTRY_STS_AP1_R 0x%02x%02x%02x%02x ERROR: CEC173x: Failed to read FLASH_IMG_VLD_RTRY_STS_AP0_R INFO: CEC173x:FLASH_IMG_VLD_RTRY_STS_AP0_R 0x%02x%02x%02x%02x ERROR: CEC173x: Failed to read BOOT_IMAGE_STATUS_R INFO: CEC173x:BOOT_IMAGE_STATUS_R 0x%02x k k $l l Lm m n Po o I 2)( 9__WO{ v >D @ ) W RS 9 **^ * * 4. qA T3 2tR @9 q T 2 * T 2 0
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9w 9 i .=D ! ? 2{COBWA_Ĩ_sbl %s: Unsupported partition %s attestate_partition_open %s: Open partition %s with status= %d %s: Error on Calculating CRC = %d attestate_partition_progress %s: CRC not calculated for partition = %d attestate_crc_get %s: Calculated CRC val = %d AIC. .DC. %s: SBL version: %d,%d,%d,%d attestate_partition_send_version %s: Unable to read SBL version O{C L ` 4 2 hfA j*@lN@I}@K`m} } Tk 2 *{AO¨_og_WO{CC { * {?D s vV@ * qa T 2` q iI)jV@ * * *kRA
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ERROR: %s: PVS context has not been initialized pvs_boot_init WARNING: %s: pvs_flash_boot_init() failed pvs_init_with_defaults ERROR: %s: default variable store header is not valid pvs ERROR: %s: Failed to open partition %s INFO: Variable cnt scanned =%d, variable on .bin = %d pvs_init ERROR: %s: FLASH context initialized failed pvs_read pvs_write ERROR: %s: failed to initialize synchronization object pvs_context_init WO{ C v >D * @ ` *h #=D** ?tF9u@ * {BOAWè_/
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ICB_RemapEx() failed with error code: %d Remapped addresses ddr_cs0 is 0x%llx, ddr_cs1 is 0x%llx p p @ @
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DDR ECC on ddr instance = %d ddr_start_addr: 0x%llx ddr_end_addr: 0x%llx synd_start_addr: 0x%llx base_addr: 0x%llx syn_addr: 0x%llx llcc -Tag RAM ecc error detected
DB ecc total count 0x%x,SB ecc total count 0x%x
LLCC%d DB count:0x%x, SB count:0x%x
Ways in which double bit errors occurred=0x%x
DB error syn : syn0=0x%08x,syn1=0x%08x,syn2=0x%08x
syn3=0x%08x,syn4=0x%08x,syn5=0x%08x
Ways in which single bit errors occurred=0x%x
SB error syn : syn0=0x%08x,syn1=0x%08x,syn2=0x%08x
llcc - Data RAM ecc error detected
LLCC%d DB count 0x%x, SB count 0x%x
syn6=0x%08x,syn7=0x%08x
No llcc ecc errors has been recorded
BROADCAST_LLCC_DRP_SRAM_STATUS = 0x%08x
BROADCAST_LLCC_DRP_FIFO_EMPTY_STATUS = 0x%08x
BROADCAST_LLCC_DRP_FIFO_FULL_STATUS = 0x%08x
BROADCAST_LLCC_DRP_PCBSLP_STATUS = 0x%08x
BROADCAST_LLCC_DRP_PCB_CMD_STATUS = 0x%08x
BROADCAST_LLCC_DRP_VALID_STATUS = 0x%08x
BROADCAST_LLCC_DRP_READY_STATUS = 0x%08x
BROADCAST_LLCC_DRP_RAMSLP_STATUS = 0x%08x
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>================ READ INITIAL VREF TRAINING START ================<
Frequency, %d, Channel, %d,
Channel - %d Rank - %d
>================ READ INITIAL VREF TRAINING END ================<
copy READ CDC from rank 0 to rank 1 in prfs %d
>================ READ TRAINING START ================<
DDRSS_rd_dqdqs_1D_pbcf, rank, %d
dual_rank if for read, ch %d rank, %d
DDRSS_rd_Vref_1D_hprx, both rank,
DDRSS_rd_dqdqs_1D_cf, rank, %d
DDRSS_rd_Vref_1D_mprx, both rank,
>================ READ TRAINING END ================<
RD_DQS_DCD RD_DQ_DCD perbit delay greater than 15 for %d : %d
PHY_DQ_%d,midp, %d,coarse, %d, fine, %d,
%3d, SLT Print, RD_PHY_BIT ,%d ,%d ,%d ,
SLT Print, RD_PASS_START ,%d ,%d ,%d ,
SLT Print, RD_PASS_STOP ,%d ,%d ,%d ,
SLT Print, RD_PASS_MIDP ,%d ,%d ,%d ,
SLT Print, RD_PASS_EYEW ,%d ,%d ,%d ,
SLT Print, RD_PBIT_DELAY ,%d ,%d ,%d ,
pr_bus_eyew[%d](ps)=, %d ,
pr_bus_skwr[%d](ps)=, %d ,
DDR ABORT: RD 1D PBCF ZERO EYE WIDTH, Frequency = %d, Channel = %d, Rank = %d, PHY_Byte = %d, Bit = %d
DDR ABORT: RD 1D CF ZERO EYE WIDTH, Frequency = %d, Channel = %d, Rank = %d, PHY_Byte = %d, Bit = %d
RD_EYE_WIDTH VREF_TRAIN RD_EYE_WIDTH_SETUP RD_EYE_WIDTH_HOLD strt= %d, stop= %d , eyew= %d (%d ps) ,
PHY_DQ%d,midp, %d, coarse, %d, fine, %d, Delay(ps), %d,
pr_bus_eyew[%d](ps)=, %d ,
Max VREF : %d
DDR ABORT: RD 2D SWEEP ZERO EYE HEIGHT, Frequency = %d, Channel = %d, Rank = %d, Byte = %d
RD_2D_VREF
Case : 4
DDR ABORT: RD 1D HPRX ZERO EYE HEIGHT, Frequency = %d, Channel = %d, Rank = %d, PHY_Byte = %d, Bit = %d
RD_EYE_HEIGHT_HPVREF RD_EYE_HEIGHT_HPVREF_MID_TOP RD_EYE_HEIGHT_HPVREF_MID_BOT Rank, %d,
PHY_DQ_%d,GlobalVref_in_CA[%d], %d,
%4d, bit
PHY_bit
%s,
local vref pr_bus_eyew[ca%d]=, %d ,
pr_bus_skwr[ca%d]=, %d ,
DDR ABORT: RD 1D MPRX ZERO EYE HEIGHT, Frequency = %d, Channel = %d, Rank = %d, Byte = 0&1
RD_EYE_HEIGHT_MPVREF RD_EYE_HEIGHT_MPVREF_MID_TOP RD_EYE_HEIGHT_MPVREF_MID_BOT failed to set Vref
, PHY_Byte = %d, EYE width = %d (ps) = %d (f steps)
passing region start passing region stop passing region midp passing region eyew RD_EYE_WIDTH_SIPI_+60mv RD_EYE_WIDTH_SIPI_-60mv RD_EYE_WIDTH_MASK_TOP RD_EYE_WIDTH_MASK_BOTTOM VREF_SIPI+ VREF_SIPI- VREF_TOP VREF_BOTTOM og_WO{Cї / >D2 **\ hRmiR9 %}B kH T)B MF9*} S_7qd)@z TkR9 @ q iA T?k T R !?* * * ** b>Fy !4 * ! * 2 ?k! T R !?* * * **z b>Fy !4 * ! * a T 2 j @y RG@~@ A 2"i
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>================ WRITE TRAINING START ================<
Frequency, %d, Channel, %d, Rank, %d,
>================ WRITE TRAINING END ================<
DDRSS_wr_dqdqs_2D_vcf 1st run
DDRSS_wr_dqdqs_1D_pbcf
DDRSS_wr_dqdqs_1D_cf
DDRSS_wr_dqdqs_2D_vcf_max_rec
Copied Vref from highest Freq
DBI offset: %d
Try next DBI offset PHY_DQ%d,knob, %d, coarse, %d, fine, %d, delay, %d,
dbi, memory bit,
SLT Print, WR_PHY_BIT ,%d ,%d ,%d , PHY_bit,
SLT Print, WR_PASS_START ,%d ,%d ,%d ,
SLT Print, WR_PASS_STOP ,%d ,%d ,%d ,
SLT Print, WR_PASS_MIDP ,%d ,%d ,%d ,
SLT Print, WR_PASS_EYEW ,%d ,%d ,%d ,
SLT Print, WR_PBIT_DELAY ,%d ,%d ,%d ,
pr_bus_eyew[%d]=, %d , ps, %d,
pr_bus_skwr[%d]=, %d , ps, %d,
WR_DQS_DCD WR_DQ_DCD WR_EYE_WIDTH WR_EYE_WIDTH_SETUP WR_EYE_WIDTH_HOLD PHY_DQ%d,strt= %d, stop= %d , eyew= %d (%d ps) ,
PHY_DQ%d,
dqsdcc_adj_cur= %4d, dqsdcc_adj_otp= %4d, dqsdcc_adj_set= %4d,
dq_dcc_adj_cur= %4d, dq_dcc_adj_otp= %4d, dq_dcc_adj_set= %4d,
ZERO_EYE_WIDTH WR_EYE_WIDTH_MASK_TOP VREF_TOP WR_EYE_WIDTH_MASK_BOT VREF_BOTTOM WR_EYE_HEIGHT WR_EYE_HEIGHT_MID_TOP WR_EYE_HEIGHT_MID_BOT PHY_DQ, %d,
vmin, %d,vmax, %d mid_v(Dec): %d, vref_data(Hex): %x
mid_cdc, %d, coarse, %d, fine, %d, delay, %d,
WR_EYE_WIDTH_SIPI_+60mv VREF_SIPI+ WR_EYE_WIDTH_SIPI_-60mv VREF_SIPI- SCALE : Source delay %d ps Target delay %d ps
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END: DCC training
Active DCC PLL %x
Channel %u Byte %u WRLVL DQS DCC Adjustment: %x
DCC loop count = %d
WRLVL_DQS_DCC Channel %u Byte %u WR90 DQS DCC Adjustment: %x
WR90_DQS_DCC TMIN_DQS_DCC Channel %u Byte %u IO DQS DCC Adjustment: %x
IO_DQS_DCC Channel %u CA %u WRLVL CK DCC Adjustment: %x
WRLVL_CK_DCC Channel %u CA %u WR90 CK DCC Adjustment: %x
WR90_CK_DCC TMIN_CK_DCC Channel %u CA %u IO CK DCC Adjustment: %x
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Ch = %d,Rank = %d, PHY_Byte = %d:
Num_cycles: %d, Coarse_cdc: %d, Fine_cdc: %d, search_value in ps = %d
PRSF = %d Channel %d rank = %d PHY_byte_lane = %d: tDQSCKin_full_cycle = %d
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SCALE ch = %d PHY_byte = %d scaled prfs = %d Coarse = %d Fine = %d Half = %d
Write window start = 0%d Vref= %d, start= %d, Stop= %d
Area=%d
top=%d
bottom=%d
left=%d
right=%d
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cdc=%d
%d,%d,%d,%d,%d,%d,READ ,00ff,00ff,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
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,0000,0000,00ff,00ff,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
,0000,0000,ff00,ff00,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
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,0000,0000,0000,0000,ff00,ff00,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
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,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,00ff,00ff
,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,ff00,ff00
SuperIteration Loop Repeat,Frequency,PLL,MP Vref,RD90 Coarse,RD90 Fine,Read/Write, CH0 CS0 P0,CH0 CS0 P1,CH0 CS1 P0,CH0 CS1 P1, CH1 CS0 P0,CH1 CS0 P1,CH1 CS1 P0,CH1 CS1 P1, CH2 CS0 P0,CH2 CS0 P1,CH2 CS1 P0,CH2 CS1 P1, CH3 CS0 P0,CH3 CS0 P1,CH3 CS1 P0,CH3 CS1 P1, CH4 CS0 P0,CH4 CS0 P1,CH4 CS1 P0,CH4 CS1 P1, CH5 CS0 P0,CH5 CS0 P1,CH5 CS1 P0,CH5 CS1 P1, CH6 CS0 P0,CH6 CS0 P1,CH6 CS1 P0,CH6 CS1 P1, CH7 CS0 P0,CH7 CS0 P1,CH7 CS1 P0,CH7 CS1 P1, CH8 CS0 P0,CH8 CS0 P1,CH8 CS1 P0,CH8 CS1 P1, CH9 CS0 P0,CH9 CS0 P1,CH9 CS1 P0,CH9 CS1 P1, CH10 CS0 P0,CH10 CS0 P1,CH10 CS1 P0,CH10 CS1 P1, CH11 CS0 P0,CH11 CS0 P1,CH11 CS1 P0,CH11 CS1 P1, CH12 CS0 P0,CH12 CS0 P1,CH12 CS1 P0,CH12 CS1 P1, CH13 CS0 P0,CH13 CS0 P1,CH13 CS1 P0,CH13 CS1 P1, CH14 CS0 P0,CH14 CS0 P1,CH14 CS1 P0,CH14 CS1 P1, CH15 CS0 P0,CH15 CS0 P1,CH15 CS1 P0,CH15 CS1 P1
Trained record start ddi_param_count wr %d Trained record Completed Plot record Start %d %d %d %04x %04x Plot record Completed %d,%d,%d,%d,%d,%d,WRITE ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,00ff,00ff,0000,0000 0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000
,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000 ,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,ff00,ff00,0000,0000
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flash_partition_get_gpt %s: Invalid backup partition table
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%s: Valid primary and invalid backup partition table
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%s: GPT array size requires more blocks than available %s: Partition Array Allocate pool error
%s: Partition Entry ReadBlocks error
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All GPT array entries are unused
%s: GPT Array Allocate pool error
%s: Allocate pool error
PartitionValidGptTable Invalid efi partition table header
%s: Size > MaxSize
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%s: Crc check failed
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%s: GPT doesn't match defaults and will not be updated PartitionUpdateGptTable %s: Detecting %d missing partition table entries (%d avail)
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